`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   13:55:05 12/09/2013
// Design Name:   IT_module
// Module Name:   D:/Jayvee/H_264_Decoder/IT_module_test.v
// Project Name:  H_264_Decoder
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: IT_module
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module IT_module_test;

	// Inputs
	reg gClk_it;
	reg Rst;
	reg DCT_or_HDT;
	reg isChroDC;
	reg isDirect;
	reg [15:0] Input_0;
	reg [15:0] Input_1;
	reg [15:0] Input_2;
	reg [15:0] Input_3;
	reg [15:0] Input_4;
	reg [15:0] Input_5;
	reg [15:0] Input_6;
	reg [15:0] Input_7;
	reg [15:0] Input_8;
	reg [15:0] Input_9;
	reg [15:0] Input_10;
	reg [15:0] Input_11;
	reg [15:0] Input_12;
	reg [15:0] Input_13;
	reg [15:0] Input_14;
	reg [15:0] Input_15;
    reg [4:0] cnt;
	// Outputs
	wire [15:0] Output_0;
	wire [15:0] Output_1;
	wire [15:0] Output_2;
	wire [15:0] Output_3;
	wire [15:0] Output_4;
	wire [15:0] Output_5;
	wire [15:0] Output_6;
	wire [15:0] Output_7;
	wire [15:0] Output_8;
	wire [15:0] Output_9;
	wire [15:0] Output_10;
	wire [15:0] Output_11;
	wire [15:0] Output_12;
	wire [15:0] Output_13;
	wire [15:0] Output_14;
	wire [15:0] Output_15;

	// Instantiate the Unit Under Test (UUT)
	IT_module uut (
		//.gClk_it(gClk_it), 
		//.Rst(Rst), 
		.DCT_or_HDT(DCT_or_HDT), 
		.isChroDC(isChroDC), 
		.isDirect(isDirect), 
		.Input_0(Input_0), 
		.Input_1(Input_1), 
		.Input_2(Input_2), 
		.Input_3(Input_3), 
		.Input_4(Input_4), 
		.Input_5(Input_5), 
		.Input_6(Input_6), 
		.Input_7(Input_7), 
		.Input_8(Input_8), 
		.Input_9(Input_9), 
		.Input_10(Input_10), 
		.Input_11(Input_11), 
		.Input_12(Input_12), 
		.Input_13(Input_13), 
		.Input_14(Input_14), 
		.Input_15(Input_15), 
		.Output_0(Output_0), 
		.Output_1(Output_1), 
		.Output_2(Output_2), 
		.Output_3(Output_3), 
		.Output_4(Output_4), 
		.Output_5(Output_5), 
		.Output_6(Output_6), 
		.Output_7(Output_7), 
		.Output_8(Output_8), 
		.Output_9(Output_9), 
		.Output_10(Output_10), 
		.Output_11(Output_11), 
		.Output_12(Output_12), 
		.Output_13(Output_13), 
		.Output_14(Output_14), 
		.Output_15(Output_15)
	);

	initial begin
		// Initialize Inputs
		gClk_it = 0;
		Rst = 0;
        cnt = 0;
		DCT_or_HDT = 0;
		isChroDC = 0;
		isDirect = 0;
		Input_0 = 0;
		Input_1 = 0;
		Input_2 = 0;
		Input_3 = 0;
		Input_4 = 0;
		Input_5 = 0;
		Input_6 = 0;
		Input_7 = 0;
		Input_8 = 0;
		Input_9 = 0;
		Input_10 = 0;
		Input_11 = 0;
		Input_12 = 0;
		Input_13 = 0;
		Input_14 = 0;
		Input_15 = 0;

		// Wait 100 ns for global reset to finish
		#100;
        #10 Rst = 1;
		// Add stimulus here

	end
    always #20 gClk_it=~gClk_it;
    
    always @(posedge gClk_it or negedge Rst) begin
        if(!Rst) begin
            cnt <= 0;
        end
        else begin
            case(cnt)
            0:begin
                DCT_or_HDT <= 1;
                isChroDC <= 0;
                isDirect <= 0;
                Input_0 <= 1;
                Input_1 <= 2;
                Input_2 <= 3;
                Input_3 <= 4;
                Input_4 <= 5;
                Input_5 <= 6;
                Input_6 <= 7;
                Input_7 <= 8;
                Input_8 <= 9;
                Input_9 <= 10;
                Input_10 <= 11;
                Input_11 <= 12;
                Input_12 <= 13;
                Input_13 <= 14;
                Input_14 <= 15;
                Input_15 <= 16;
                cnt <= cnt + 1;
            end
            1:begin
                DCT_or_HDT <= 1;
                isChroDC <= 0;
                isDirect <= 1;
                Input_0 <= 1;
                Input_1 <= 2;
                Input_2 <= 3;
                Input_3 <= 4;
                Input_4 <= 5;
                Input_5 <= 6;
                Input_6 <= 7;
                Input_7 <= 8;
                Input_8 <= 9;
                Input_9 <= 10;
                Input_10 <= 11;
                Input_11 <= 12;
                Input_12 <= 13;
                Input_13 <= 14;
                Input_14 <= 15;
                Input_15 <= 16;
                cnt <= cnt + 1;
            end
            2:begin
                cnt <= cnt;
            end
            endcase
        end
    end
endmodule

